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STK14EC8
Preliminary
FEATURES
* 15, 25, 45 ns Read Access and R/W Cycle Time * Unlimited Read/Write Endurance * Automatic Non-volatile STORE on Power Loss * Non-Volatile STORE Under Hardware or Software Control * Automatic RECALL to SRAM on Power Up * Unlimited RECALL Cycles * 200K STORE Endurance * 20-Year Non-volatile Data Retention * Single 3.0V +20%, -10% Operation * Commercial, Industrial Temperatures * 44-pin 400-mil TSOPII (RoHS-Compliant) * 48-ball Fine Pitch Ball Grid Array (FBGA)
512Kx8 Autostore nvSRAM
DESCRIPTION
The Simtek STK14EC8 is a 4MB fast static RAM with a non-volatile Quantum Trap storage element included with each memory cell. The SRAM provides the fast access & cycle times, ease of use and unlimited read & write endurance of a normal SRAM. Data transfers automatically to the non-volatile storage cells when power loss is detected (the STORE operation). On power up, data is automatically restored to the SRAM (the RECALL operation). Both STORE and RECALL operations are also available under software control. The Simtek nvSRAM is the highest performance, most reliable non-volatile memory available.
BLOCK DIAGRAM
VCC A0 A1 A2 A3 A4 A5 A6 A7 A8 A17 A18 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Quantum Trap 2048 X 2048 ROW DECODER STORE STATIC RAM ARRAY 2048 X 2048 RECALL STORE/ RECALL CONTROL VCAP
POWER CONTROL
HSB
SOFTWARE DETECT INPUT BUFFERS COLUMN I/O COLUMN DEC
A18 - A0
A 9 A 10 A 11 A 12 A 13 A14 A15 A16
G E W
This is a product in development that has fixed target specifications that are subject to change pending characterization results. Simtek Confidential & Proprietary
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STK14EC8
NC NC A0 A1 A2 A3 A4 E DQ0 DQ1 VCC VSS DQ2 DQ3 W A5 A6 A7 A8 A9 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 (TOP) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 HSB NC NC A18 A17 A16 A15 G DQ7 DQ6 VSS VCC DQ5 DQ4 VCAP A14 A13 A12 A11 A10 NC NC
Preliminary
1 NC NC DQ0 VSS VCC DQ3 NC A18
2 G NC NC DQ1
3 A0 A3 A5 A17
4 A1 A4 A6 A7 A16 A15 A13 A10
5 A2 E NC DQ5 DQ6 NC W A11
6 NC NC DQ4 VCC VSS DQ7 NC NC A B C D E F G H
DQ2 VCAP NC HSB A8 A14 A12 A9
(TOP)
48-Ball FBGA (See mechanical drawing on page 18)
44-Pin TSOP-II (See mechanical drawing on page 17)
PIN DESCRIPTIONS
Pin Name A18-A0 DQ7-DQ0 E W G VCC HSB Input I/O Input Input Input Power Supply I/O I/O Description Address: The 19 address inputs select one of 524,288 bytes in the nvSRAM array Data: Bi-directional 8-bit data bus for accessing the nvSRAM Chip Enable: The active low E input selects the device Write Enable Input, Active Low: When selected low, enables data on the IO pins to be written to the address location latched by the falling edge of CE. Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high causes the DQ pins to tri-state. Power: 3.0V, +20%, -10% Hardware Store Busy: When low this output indicates a Store is in progress (also low during power up while busy). When pulled low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor keeps this pin high if not connected. (Connection Optional). Autostore Capacitor: Supplies power to the nvSRAM during a power loss to store data from SRAM to nonvolatile storage elements. Ground This pin is not connected to the die. (Do not connect in design; reserved for future use)
VCAP VSS NC
Power Supply Power Supply No Connect
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Preliminary
ABSOLUTE MAXIMUM RATINGSa
Voltage on Input Relative to Ground . . . . . . . . . . . . . -0.5V to 4.1V Voltage on Input Relative to VSS . . . . . . . . . .-0.5V to (VCC + 0.5V) Voltage on DQ0-7 or HSB . . . . . . . . . . . . . . . .-0.5V to (VCC + 0.5V) Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .-55C to 125C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .-55C to 140C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to 150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
STK14EC8
Note a: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TF (TSOP-II 44) PACKAGE THERMAL CHARACTERISTICS
jc tbd; ja tbd [0fpm], tbd [200fpm], tbd C/W [500fpm].
BF (FBGA48) PACKAGE THERMAL CHARACTERISTICS
jc tbd C/W; ja tbd [0fpm], tbd [200fpm], tbd C/W [500fpm].
DC CHARACTERISTICS
COMMERCIAL SYMBOL ICC1 PARAMETER MIN Average VCC Current 70 65 50 75 70 52 mA mA mA MAX MIN MAX INDUSTRIAL UNITS
(VCC = 2.7V-3.6V)
NOTES
tAVAV = 15ns tAVAV = 25ns tAVAV = 45ns Dependent on output loading and cycle rate. Values obtained without output loads. All Inputs Don't Care, VCC = max Average current for duration of STORE cycle (tSTORE) W (V CC - 0.2V) All Other Inputs Cycling at CMOS Levels Dependent on output loading and cycle rate. Values obtained without output loads. All Inputs Don't Care Average current for duration of STORE cycle (tSTORE) E (VCC -0.2V) All Others VIN 0.2V or (VCC-0.2V) Standby current level after nonvolatile cycle complete VCC = max VIN = VSS to VCC VCC = max VIN = VSS to VCC, E or G VIH All Inputs All Inputs IOUT = - 2mA (except HSB) IOUT = 4mA
ICC2
Average VCC Current during STORE 6 6 mA
ICC3
Average VCC Current at tAVAV = 200ns 3V, 25C, Typical 13 13 mA
ICC4
Average VCAP Current during AutoStoreTM Cycle VCC Standby Current (Standby, Stable CMOS Levels)
6
6
mA
ISB
3
3
mA
IILK IOLK VIH VIL VOH VOL TA VCC VCAP NVC DATAR
Input Leakage Current Off-State Output Leakage Current Input Logic "1" Voltage Input Logic "0" Voltage Output Logic "1" Voltage Output Logic "0" Voltage Operating Temperature Operating Voltage Storage Capacitance Nonvolatile STORE operations Data Retention 0 2.7 61 200 20 2.0 VSS -0.5 2.4
1 1 VCC + 0.5 0.8 2.0 VSS -0.5 2.4 0.4 70 3.6 82 -40 2.7 61 200 20
1 1 VCC + 0.5 0.8
A A V V V
0.4 85 3.6 180
V C V F K Years
3.0V nominal Between VCAP pin and VSS, 5V rated (Nom. 68 F to 150 F +20%, - 10%)
@ 55 deg C
Note: The HSB pin has IOUT = -10 uA for VOH of 2.4 V. This parameter is characterized but not tested.
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STK14EC8
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 and 2
Preliminary
CAPACITANCEb
SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance
(TA = 25C, f = 1.0MHz)
MAX 7 7 UNITS pF pF CONDITIONS V = 0 to 3V V = 0 to 3V
Note b: These parameters are guaranteed but not tested.
3.0V
577 Ohms OUTPUT 789 Ohms 30 pF INCLUDING SCOPE AND FIXTURE
Figure 1: AC Output Loading
3.0V
577 Ohms OUTPUT 789 Ohms 5 pF INCLUDING SCOPE AND FIXTURE
Figure 2: AC Output Loading for Tristate Specs (tHZ, tLZ, tWLQZ, tWHQZ, tGLQX, tGHQZ)
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Preliminary
SRAM READ CYCLES #1 & #2
SYMBOLS NO. #1 1 2 3 4 5 6 7 8 9 10 11 tAXQXd tAVAVc tAVQVd #2 tELQV tELEH
c d
STK14EC8
STK14EC8-15 PARAMETER Alt. tACS tRC tAA tOE
d
STK14EC8-25 MIN MAX 25 25
STK14EC8-45 UNITS MIN MAX 45 45 ns ns 45 20 3 3 ns ns ns ns 15 0 ns ns 15 0 ns ns 45 ns
MIN Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold after Address Change Address Change or Chip Enable to Output Active Address Change or Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby 0 0 3 3 15
MAX 15
tAVQV
15 10 3 3 7 0 7 0 15
25 12
tGLQV tAXQX tELQX tEHQZe tGLQX tGHQZ
e b
tOH tLZ tHZ tOLZ tOHZ tPA tPS
10
10
tELICCH
tEHICCLb
25
Note c: Note d: Note e: Note f:
W must be high during SRAM READ cycles. Device is continuously selected with E and G both low Measured 200mV from steady state output voltage. HSB must remain high during READ and WRITE cycles.
SRAM READ CYCLE #1: Address Controlledc,d,f
2 tAVAV ADDRESS 5 tAXQX DQ (DATA OUT)
DATA VALID
3 tAVQV
SRAM READ CYCLE #2: E and G Controlledc,f
ADDR ESS t E LE H 1 tEL Q V
2 29
tEHAX 11 tEHI CC L 7 tEHQ Z
E
27
6 t ELQ X
G
t AV QV 4 t G L QV 9 tGH Q Z
3
8 tG L Q X DQ (D ATA OUT) 10 tELI CC H
DAT A VAL ID
AC T IVE
ICC
ST AND BY
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STK14EC8
SRAM WRITE CYCLES #1 & #2
SYMBOLS NO. #1 #2 Alt. PARAMETER MIN MAX STK14EC8-15
Preliminary
STK14EC8-25 MIN MAX
STK14EC8-45 UNITS MIN MAX
12 13 14 15 16 17 18 19 20 21
tAVAV tWLWH tELWH tDVWH tWHDX tAVWH tAVWL tWHAX t WLQZ
e, g
tAVAV tWLEH tELEH tDVEH tEHDX tAVEH tAVEL tEHAX
tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW
Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Set-up to End of Write Data Hold after End of Write Address Set-up to End of Write Address Set-up to Start of Write Address Hold after End of Write Write Enable to Output Disable Output Active after End of Write
15 10 15 5 0 10 0 0 7 3
25 20 20 10 0 20 0 0 10 3
45 30 30 15 0 30 0 0 15 3
ns ns ns ns ns ns ns ns ns ns
tWHQX
Note g: If W is low when E goes low, the outputs remain in the high-impedance state. Note h: E or W must be VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledg,h
12 tAVAV ADDRESS 14 tELWH E 17 tAVWH 13 tWLWH 15 tDVWH DATA IN 20 tWLQZ DATA OUT
PREVIOUS DATA HIGH IMPEDANCE DATA VALID
19 tWHAX
18 tAVWL W
16 tWHDX
21 tWHQX
SRAM WRITE CYCLE #2: E Controlledg,h
12 tAVAV ADDRESS 18 tAVEL E 14 tELEH 19 tEHAX
17 tAVEH W
13 tWLEH 15 tDVEH 16 tEHDX
DATA VALID HIGH IMPEDANCE
DATA IN DATA OUT
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Preliminary
AutoStoreTM/POWER-UP RECALL
SYMBOLS NO. Standard Alternate PARAMETER MIN
STK14EC8
STK14EC8 UNITS MAX NOTES
22 23 24 25
tHRECALL tSTORE VSWITCH VCCRISE tHLHZ
Power-up RECALL Duration
STORE Cycle Duration
20 12.5 2.65 150
ms ms V
s
i j
Low Voltage Trigger Level VCC Rise Time
Note i: Note j:
tHRECALL starts from the time VCC rises above VSWITCH If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place
AutoStoreTM/POWER-UP RECALL
STORE occurs only if a SRAM write has happened. No STORE occurs without at least one SRAM write.
VCC 24 VSWITCH
25 tVCCRISE
AutoStoreTM
23 tSTORE 23 tSTORE
POWER-UP RECALL
22 tHRECALL
22 tHRECALL
Read & Write Inhibited
POWER-UP RECALL
BROWN OUT TM AutoStore
POWER-UP RECALL
POWER DOWN TM AutoStore
Note: Read and Write cycles will be ignored during STORE, RECALL and while VCC is below VSWITCH
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STK14EC8
SOFTWARE-CONTROLLED STORE/RECALL CYCLEk,l
Symbols NO. E Contk G Contk PARAMETER Alternate MIN STORE/RECALL Initiation Cycle Time MAX MIN STK14EC8-15
Preliminary
STK14EC8-25 MAX
STK14EC8-45 UNITS NOTES MIN MAX
26 27 28 29 30
tAVAV tAVEL tELEH tEHAX tRECALL
tAVAV tAVGL tGLGH tGHAX tRECALL
tRC tAS tCW
15 0 12 1 150
25 0 20 1 150
45 0 30 1 150
ns ns ns ns
s
Address Set-up Time Clock Pulse Width Address Hold Time
RECALL Duration
l
Note k: The software sequence is clocked on the falling edge of E controlled READs or G controlled READs Note l: The six consecutive addresses must be read in the order listed in the Software STORE/RECALL Mode Selection Table. W must be high during all six consecutive E or G controlled cycles.
SOFTWARE STORE/RECALL CYCLE: E CONTROLLEDl
26 tAVAV ADDRESS 27 tAVEL
ADDRESS #1
26 tAVAV
ADDRESS #6
E
28 tELEH
29 tEHAX
G
23 tSTORE DQ (DATA)
DATA VALID DATA VALID
/t
30
RECALL
HIGH IMPEDENCE
SOFTWARE STORE/RECALL CYCLE: G CONTROLLEDl
26 tAVAV ADDRESS
ADDRESS #1
26 tAVAV
ADDRESS #6
E
27 tAVGL
28 tGLGH
G
23 tSTORE
/
29 tGHAX DQ (DATA)
DATA VALID DATA VALID
30 tRECALL
HIGH IMPEDENCE
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Preliminary
HARDWARE STORE CYCLE
SYMBOLS PARAMETER Standard Alternate MIN
STK14EC8
STK14EC8 UNITS MAX NOTES
31 1 32 2
tDELAY tHLHX
tHLQZ
Hardware STORE to SRAM Disabled Hardware STORE Pulse Width
t
.05 15
70
s
m
ns
Note m: On a hardware STORE initiation, SRAM operation continues to be enabled for time DELAY to allow read/write cycles to complete
HARDWARE STORE CYCLE
32 t HLHX
HSB (IN)
23 t STORE
HSB (OUT)
31
tDELAY
DQ (DATA OUT)
SRAM Enabled
SRAM Enabled
Soft Sequence Commands
NO. SYMBOLS Standard PARAMETER STK14EC8 MIN Soft Sequence Processing Time MAX UNITS NOTES
33
tSS
70
s
n,o
Note n: This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command. Note o: Commands like Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.
33 tss
Soft Sequence Command ADDRESS
ADDRESS #1 ADDRESS #6
33 tss
Soft Sequence Command
ADDRESS #1 ADDRESS #6
Vcc
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STK14EC8
MODE SELECTION
E
H L L
Preliminary
W
X H L
G
X L X
A18-A0
X X X 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x08B45 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x04B46 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x08FC0 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x04C63
Mode
Not Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Enable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Store Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall
I/O
Output High Z Output Data Input Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z
Power
Standby Active Active
Notes
L
H
L
Active
q,r,s
L
H
L
Active
q,r,s
L
H
L
Active
q,r,s
ICC2
L
H
L
Active
q,r,s
Note q: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. Note r: While there are 19 addresses on the STK14EC8, only the lower 16 are used to control software modes Note s: I/O state depends on the state of G. The I/O table shown assumes G low
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Preliminary
STK14EC8
nvSRAM OPERATION
SRAM WRITE
A WRITE cycle is performed whenever E and W are low and HSB is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low.
nvSRAM
The STK14EC8 nvSRAM is made up of two functional components paired in the same physical cell. These are the SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates like a standard fast static RAM. Data in the SRAM can be transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture allows all cells to be stored and recalled in parallel. During the STORE and RECALL operations SRAM READ and WRITE operations are inhibited. The STK14EC8 supports unlimited read and writes like a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to 200K STORE operations.
AutoStore OPERATION
The STK14EC8 stores data to nvSRAM using one of three storage operations. These three operations are Hardware Store (activated by HSB), Software Store (activated by an address sequence), and AutoStore (on power down). AutoStore operation is a unique feature of Simtek Quantum Trap technology that is enabled by default on the STK14EC8. During normal operation, the device will draw current from VCC to charge a capacitor connected to the VCAP pin. This stored charge will be used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part will automatically disconnect the VCAP pin from VCC. A STORE operation will be initiated with power provided by the VCAP capacitor. Figure 3 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. The voltage on the VCAP pin is driven to 3.6V by a regulator internal to the chip. Refer to the DC CHARACTERISTICS table for the size of the capacitor. A pull up should be placed on W to hold it inactive during power up. This pull-up is only effective if the W signal is tri-state during power up. Many MPU's will tristate their controls on power up. This should be verified when using the pullup. When the nvSRAM comes out on power-on-recall, the MPU must be active or the W held inactive until the MPU comes out of reset.
SRAM READ
The STK14EC8 performs a READ cycle whenever E and G are low while W and HSB are high. The address specified on pins A0-18 determine which of the 524,288 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E and G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high, or W and HSB is brought low.
vCC vCC 10K Ohm 0.1F vCAP vCAP
W
Figure 3: AutoStore Mode
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STK14EC8
To reduce unneeded nonvolatile stores, AutoStore and Hardware Store operations will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. The HSB signal can be monitored by the system to detect an AutoStore cycle is in progress.
Preliminary
READ cycles from six specific address locations in exact order. During the STORE cycle, previous data is erased and then the new data is programmed into the nonvolatile elements. Once a STORE cycle is initiated, further memory inputs and outputs are disabled until the cycle is completed. To initiate the software STORE cycle, the following READ sequence must be performed:
1 Read Address 2 Read Address 3 Read Address 4 Read Address 5 Read Address 6 Read Address 0x4E38 0x83E0 0x703F Valid READ Valid READ Valid READ
0xB1C7 Valid READ 0x7C1F Valid READ 0x8FC0 Initiate STORE Cycle
HARDWARE STORE (HSB) OPERATION
The STK14EC8 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin can be used to request a hardware STORE cycle. When the HSB pin is driven low, the STK14EC8 will conditionally initiate a STORE operation after tDELAY. An actual STORE cycle will only begin if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin has a very resistive pullup and is internally driven low to indicate a busy condition while the STORE (initiated by any means) is in progress. This pin should be externally pulled up if it is used to drive other inputs. SRAM READ and WRITE operations that are in progress when HSB is driven low or when VCC falls below Vswitch are given time to complete before the STORE operation is initiated. After AUTOSTORE or HSB goes low, the STK14EC8 will continue to allow SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations may take place. If a WRITE is in progress when HSB is pulled low, it will be allowed a time, tDELAY, to complete. However, any SRAM WRITE cycles requested after HSB goes low will be inhibited until HSB returns high. If HSB is not used, it should be left unconnected.
Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence and that G is active. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation.
SOFTWARE RECALL
Data can be transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of E controlled or G controlled READ operations must be performed:
1 Read Address 2 Read Address 3 Read Address 4 Read Address 5 Read Address 6 Read Address 0x4E38 0x83E0 0x703F 0x4C63 Valid READ Valid READ Valid READ Initiate RECALL Cycle
0xB1C7 Valid READ 0x7C1F Valid READ
HARDWARE RECALL (POWER-UP)
During power up or after any low-power condition (VCCSOFTWARE STORE
Data can be transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK14EC8 software STORE cycle is initiated by executing sequential E controlled or G controlled
Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM will once again be ready for READ or WRITE operations. The RECALL operation in no way alters the data in the nonvolatile storage elements. Care must be taken so the controlling falling edge is glitch and ring free so as not to double clock the read address.
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Preliminary
DATA PROTECTION
The STK14EC8 protects data from corruption during low-voltage conditions by inhibiting all externally initiated STORE and WRITE operations. The low-voltage condition is detected when VCCSTK14EC8
(program bugs, incoming inspection routines, etc.). * The autostore enabled/disabled feature will reset to "autostore enabled" on every power down event captured by the nvSRAM. The application firmware should disable autostore on each reset sequence that this behavior is desired. * The Vcap value specified in this datasheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the max Vcap value because the nvSRAM internal algorithm calculates Vcap charge time based on this max Vcap value. Customers that want to use a larger Vcap value to make sure there is extra store charge and store time should discuss their Vcap size selection with Simtek to understand any impact on the Vcap voltage level at the end of a tRECALL period.
NOISE CONSIDERATIONS
The STK14EC8 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1 F connected between VCC and VSS, using leads and traces that are a short as possible. As with all high-speed CMOS ICs, careful routing of power, ground, and signals will reduce circuit noise.
LOW AVERAGE ACTIVE POWER
CMOS technology provides the STK14EC8 with the benefit of power supply current that scales with cycle time. Less current will be drawn as the memory cycle time becomes longer than 50 ns. Figure 4 shows the relationship between ICC and READ/ WRITE cycle time. Worst-case current consumption is shown for commercial temperature range, VCC=3.6V, and chip enable at maximum frequency. Only standby current is drawn when the chip is disabled. The overall average current drawn by the STK14EC8 depends on the following items:
1 2 3 4 5 6 The duty cycle of chip enable The overall cycle rate for operations The ratio of READs to WRITEs The operating temperature The VCC Level I/O Loading
BEST PRACTICES
nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of the product's main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: * The non-volatile cells in this nvSRAM product are delivered from Simtek with 0x00 written in all cells. Incoming inspection routines at customer or contract manufacturer's sites will sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product's firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, etc. should always program a unique NV pattern (i.e., complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. * Power up boot firmware routines should rewrite the nvSRAM into the desired state (autostore enabled, etc.). While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently
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STK14EC8
Preliminary
PREVENTING AUTOSTORE
The AutoStore function can be disabled by initiating an AutoStore Disable sequence. A sequence of READ operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore Disable sequence, the following sequence of E controlled or G controlled READ operations must be performed:
1 Read Address 2 Read Address 3 Read Address 4 Read Address 5 Read Address 6 Read Address 0x4E38 0x83E0 0x703F 0x8B45 Valid READ Valid READ Valid READ AutoStore Disable
0xB1C7 Valid READ 0x7C1F Valid READ
Figure 4 - Current vs Cycle Time
The AutoStore can be re-enabled by initiating an AutoStore Enable sequence. A sequence of READ operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore Enable sequence, the following sequence of E controlled or G controlled READ operations must be performed:
1 Read Address 2 Read Address 3 Read Address 4 Read Address 5 Read Address 6 Read Address 0x4E38 0x83E0 0x703F 0x4B46 Valid READ Valid READ Valid READ AutoStore Enable
0xB1C7 Valid READ 0x7C1F Valid READ
If the AutoStore function is disabled or re-enabled, a manual STORE operation (Hardware or Software) needs to be issued to save the AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore enabled, but best design practice is to set the enable or disable state during each power-up sequence and not depend on this factory default condition. Simtek recommends users configure the part completely for the specific application.
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Preliminary
ORDERING INFORMATION STK14EC8-T F 45 I TR
Packing Option Blank = Tube TR = Tape and Reel Temperature Range Blank = Commercial (0 to +70 C) I = Industrial (-40 to +85 C) Access Time 15 = 15 ns 25 = 25 ns 45 = 45 ns Lead Finish F = Nickel/Palladium/Gold (Ni/Pd/Au) Package
STK14EC8
T = Plastic 44-pin 400 mil TSOP-II (32 mil pitch) B = Plastic 48-pin FBGA (Fine Pitch Ball Grid Array)
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STK14EC8
Ordering Codes
Part Number STK14EC8-TF15 STK14EC8-TF25 STK14EC8-TF45 STK14EC8-TF15TR STK14EC8-TF25TR STK14EC8-TF45TR STK14EC8-TF15I STK14EC8-TF25I STK14EC8-TF45I STK14EC8-TF15ITR STK14EC8-TF25ITR STK14EC8-TF45ITR STK14EC8-BF15 STK14EC8-BF25 STK14EC8-BF45 STK14EC8-BF15TR STK14EC8-BF25TR STK14EC8-BF45TR STK14EC8-BF15I STK14EC8-BF25I STK14EC8-BF45I STK14EC8-BF15ITR STK14EC8-BF25ITR STK14EC8-BF45ITR Description 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM TSOP44-400 TSOP44-400 TSOP44-400 TSOP44-400
Preliminary
Access Times 15 ns access time 25 ns access time 45 ns access time 15 ns access time 25 ns access time 45 ns access time 15 ns access time 25 ns access time 45 ns access time 15 ns access time 25 ns access time 45 ns access time 15 ns access time 25 ns access time 45 ns access time 15 ns access time 25 ns access time 45 ns access time 15 ns access time 25 ns access time 45 ns access time 15 ns access time 25 ns access time 45 ns access time
Temperature Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Industrial Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Industrial
3V 512Kx8 AutoStore nvSRAM TSOP44-400 3V 512Kx8 AutoStore nvSRAM TSOP44-400 3V 512Kx8 AutoStore nvSRAM TSOP44-400 3V 512Kx8 AutoStore nvSRAM TSOP44-400 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM 3V 512Kx8 AutoStore nvSRAM TSOP44-400 TSOP44-400 TSOP44-400 TSOP44-400 FBGA48 FBGA48 FBGA48 FBGA48 FBGA48 FBGA48 FBGA48 FBGA48 FBGA48 FBGA48 FBGA48 FBGA48
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Preliminary
STK14EC8
PACKAGE DIAGRAMS
44-Pin TSOPII
Top View
22 Pin 1 Index 1
0.404 0.396
()
10.262 10.058 0.470 0.455
()
11.938 11.735
23
44
0.404 0.396
()
10 .262 10 .058 0 5 0.0235 0.0160
()
0 .597 0 .406
0.0315 (0.800)
BSC
0.016 0.012
()
0 .400 0 .300 Base Plane Seating Plane 0.004 (0.10)
0.047 0.039
()
1 .194 0 .991 0.729 0.721
()
18 .517 18 .313 0.150 0.050
()
0 .0059 0 .0020
DIM = INCHES DIM = mm MIN MAX
MIN MAX
()
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Document Control #ML0060 Rev 1.1 Jan, 2008
STK14EC8
48-Ball FBGA
TOP VIEW
Preliminary
BOTTOM VIEW O0.05 M C O0.25 M CA B A1 CORNER
A1 CORNER
00.30 0.05(48X)
1
2
3
4
5
6
6
5
4
3
2
1
A B
0.75
+ +
A B C
C
10.00 0.10 10.00 0.10 5.25
D E F G H
D E
2.625
F G
+
+
+
H
A B 6.00 0.10
A
1.875 0.75 3.75 B 0.15(4x) 6.00 0.10
0.53 0.05
0.21 0.05
0.25C
0.36
SEATING PLANE C 120 MAX
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0.15C
//
Preliminary
Document Revision History Rev 1.0 Date April 2007 Change
Moved to Preliminary from Advance Information
STK14EC8
- made clear that nominal supply is 3.3V, not 3.0V (range 2.7V to 3.6V) - modified language on pin description of HSB and NC. - changed ISB from 1mA to 2mA. - changed Icc3 from 8mA to 13mA - clarified description language of Figure 3 - clarified description language of Software Recall - clarified description language of Preventing Autostore - corrected typo on Industrial temp range: -45 to -40
1.1
January 2008
Made the following changes to the document - page 1: revised block diagram - page 2: added new 48 FBGA information and added pin descriptions for pins E and W. - page 3: added thermal characteristics. In the DC Characteristics table, revised values for Icc2, Icc4, ISB, VIH, Vcc, and VCAP; and changed Industrial Max Value of VCAP to 180 and revised VCAP notes. Added "(except HSB)" to notes for Output Logic "1" Voltage. - page 5: in SRAM Read Cycles #1 & #2 table, revised parameter description for tELQX and tEHQZ and changed Symbol #2 to tELEH for Read Cycle Time; updated SRAM Read Cycle #2 timing diagram and changed title to add G controlled. - page 7: in AutoStore/Power-Up Recall table, changed max value for #23 (tSTORE) to 12.5. - page 8: in Software-Controlled Store/Recall Cycle table, revised values for tRECALL; revised the notes below the Software-Controlled Store/Recall Cycle diagram. - page 10: in Mode Selection table, changed column to A18-A0; in the values in this column, added a zero after each instance of "0x"; changed AutoStore Enable value to 0x04B46. - page 11: in Auto-Store Operation, deleted line about VCAP pin being driven to 5V by a charge pump internal to the chip. Also, added Stefan's revised text (italics show revision): "Refer to the DC CHARACTERISTICS table for the size of the capacitor." - page 12: under Hardware Store (HSB) Operation, revised first paragraph to read "The HSB pin has a very resistive pullup..." - page 13: added best practices section. - page 15: in Ordering Information, Lead Finish, replaced "Sn (Matte Tin) RoHS Compliant" with "Nickel/Palladium/Gold (Ni/Pd/Au)";, added "B = Plastic 48-pin FBGA (Fine Pitch Ball Grid Array)" to Finish. - page 16: in Ordering Codes, added ordering information for 48 FBGA and added access times column.
SIMTEK STK14EC8 Datasheet, January 2008 Copyright 2008, Simtek Corporation. All rights reserved. This datasheet may only be printed for the expressed use of Simtek Customers. No part of the datasheet may be reproduced in any other form or means without the express written permission from Simtek Corporation. The information contained in this publication is believed to be accurate, but changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its use, Simtek products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Simtek. Furthermore, Simtek does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Simtek products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Simtek against all charges. Nothing herein constitutes a license, grant or transfer of any rights to any Simtek patent, copyright, trademark, or other proprietary right.
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